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HC05J5GRS/h rev 1.1 ? motorola, inc., 1996 68hc05j5 specification (general release) ?december 11, 1996 technical operations taiwan csic group motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part.

december 11, 1996 general release specification mc68hc05j5 motorola rev 1.1 i table of contents section page section 1 general description 1.1 features ...................................................................................................... 1-1 1.2 mask options.............................................................................................. 1-2 1.3 functional pin description.................................................................. 1-4 1.3.1 vdd and vss ............................................................................................ 1-4 1.3.2 osc1, osc2/r............................................................................................ 1-4 1.3.3 reset ......................................................................................................... 1-6 1.3.4 irq .............................................................................................................. 1-6 1.3.5 pa0-pa7 ...................................................................................................... 1-6 1.3.6 pb0-pb5 ...................................................................................................... 1-7 section 2 memory 2.1 memory map ................................................................................................ 2-1 2.2 i/o and control registers ................................................................... 2-2 2.3 ram ................................................................................................................. 2-2 2.4 rom................................................................................................................. 2-2 section 3 central processing unit 3.1 registers .................................................................................................... 3-1 3.1.1 accumulator (a) ........................................................................................... 3-2 3.1.2 index register (x)........................................................................................ 3-2 3.1.3 stack pointer (sp) ....................................................................................... 3-2 3.1.4 program counter (pc)................................................................................. 3-2 3.1.5 condition code register (ccr) .................................................................. 3-3 section 4 interrupts 4.1 cpu interrupt processing ................................................................... 4-1 4.2 reset interrupt sequence .................................................................. 4-2 4.3 software interrupt (swi) ..................................................................... 4-3 4.4 hardware interrupts ............................................................................ 4-3 4.4.1 external interrupt (irq) ............................................................................... 4-3 4.4.2 irq control/status register (icsr), $0a.................................................... 4-4 4.4.3 optional external interrupts (pa0-pa3)....................................................... 4-6 4.4.4 timer interrupt (timer)............................................................................... 4-6
general release specification december 11, 1996 motorola mc68hc05j5 ii rev 1.1 table of contents section page section 5 resets 5.1 external reset (reset).......................................................................... 5-1 5.2 internal resets ........................................................................................ 5-1 5.2.1 power-on reset (por) ............................................................................... 5-1 5.2.2 computer operating properly reset (copr).............................................. 5-2 5.2.3 illegal address reset (iladr)..................................................................... 5-2 5.2.4 low voltage reset (lvr) ............................................................................ 5-2 section 6 modes of operation 6.1 mode entry ................................................................................................. 6-1 6.2 single-chip mode (scm) ........................................................................... 6-1 6.3 self-check mode....................................................................................... 6-2 6.4 low-power modes .................................................................................... 6-2 6.4.1 stop instruction ......................................................................................... 6-2 6.4.2 wait mode.................................................................................................. 6-4 6.5 data-retention mode.............................................................................. 6-4 6.6 cop watchdog timer considerations ............................................. 6-5 section 7 input/output ports 7.1 slow output falling-edge transition............................................. 7-1 7.2 port a............................................................................................................ 7-1 7.2.1 port a data register.................................................................................... 7-2 7.2.2 port a data direction register..................................................................... 7-2 7.2.3 port a pull-down/up register....................................................................... 7-3 7.2.4 port a drive capability................................................................................. 7-3 7.2.5 port a i/o pin interrupts............................................................................... 7-3 7.3 port b............................................................................................................ 7-4 7.3.1 port b data register.................................................................................... 7-5 7.3.2 port b data direction register..................................................................... 7-5 7.3.3 port b pull-down/up register....................................................................... 7-6 7.4 i/o port programming ............................................................................ 7-6 7.4.1 pin data direction........................................................................................ 7-6 7.4.2 output pin.................................................................................................... 7-6 7.4.3 input pin....................................................................................................... 7-7 7.4.4 i/o pin transitions ....................................................................................... 7-7 7.4.5 i/o pin truth tables..................................................................................... 7-7
december 11, 1996 general release specification mc68hc05j5 motorola rev 1.1 iii table of contents section page section 8 multi-function timer 8.1 timer registers ........................................................................................ 8-2 8.1.1 timer counter register (tcr), $09............................................................. 8-2 8.1.2 timer control/status register (tcsr), $08................................................. 8-3 8.2 cop watchdog timer............................................................................... 8-4 8.3 operation during stop mode .............................................................. 8-5 8.4 operation during wait/halt mode..................................................... 8-5 section 9 instruction set 9.1 register/memory instructions.......................................................... 9-1 9.2 read-modify-write instructions ....................................................... 9-2 9.3 branch instructions .............................................................................. 9-2 9.4 bit manipulation instructions............................................................ 9-3 9.5 control instructions............................................................................ 9-3 9.6 addressing modes ................................................................................... 9-3 9.6.1 immediate .................................................................................................... 9-4 9.6.2 direct ........................................................................................................... 9-4 9.6.3 extended...................................................................................................... 9-4 9.6.4 relative........................................................................................................ 9-4 9.6.5 indexed, no offset....................................................................................... 9-4 9.6.6 indexed, 8-bit offset .................................................................................... 9-5 9.6.7 indexed, 16-bit offset .................................................................................. 9-5 9.6.8 bit set/clear................................................................................................. 9-5 9.6.9 bit test and branch ..................................................................................... 9-5 9.6.10 inherent........................................................................................................ 9-5 section 10 electrical specifications 10.1 maximum ratings..................................................................................... 10-1 10.2 thermal characteristics ................................................................... 10-1 10.3 dc electrical characteristics........................................................ 10-2 10.4 control timing ........................................................................................ 10-3 section 11 mechanical specification 11.1 16-pin plastic dual-in-line package (pdip) ..................................... 11-1 11.2 16-pin small outline intergrated circuit (soic) ........................ 11-2 11.3 20-pin plastic dual-in-line package (pdip) ..................................... 11-2 11.4 20-pin small outline intergrated circuit (soic) ........................ 11-3
general release specification december 11, 1996 motorola mc68hc05j5 iv rev 1.1 table of contents section page
december 11, 1996 general release specification mc68hc05j5 motorola rev 1.1 v list of figures figure title page 1-1 mc68hc05j5 block diagram ......................................................................... 1-2 1-2 pin assignments for 16-pin package............................................................... 1-3 1-3 pin assignments for 20-pin package............................................................... 1-3 1-4 oscillator connections ..................................................................................... 1-5 2-1 mc68hc05j5 memory map............................................................................ 2-1 2-2 i/o registers memory map ............................................................................. 2-2 2-3 i/o registers $0000-$000f............................................................................. 2-3 2-4 i/o registers $0010-$001f............................................................................. 2-4 3-1 mc68hc05 programming model ..................................................................... 3-1 4-1 interrupt processing flowchart ........................................................................ 4-2 4-2 irq status & control register ......................................................................... 4-4 6-1 stop/halt/wait flowcharts......................................................................... 6-3 7-1 port b data direction register ......................................................................... 7-1 7-2 port a i/o circuitry ........................................................................................... 7-2 7-3 port b i/o circuitry ........................................................................................... 7-4 8-1 multi-function timer block diagram ................................................................ 8-1 8-2 timer counter register.................................................................................... 8-2 8-3 timer control/status register (tcsr)............................................................. 8-3 8-4 cop watchdog timer location ....................................................................... 8-5
general release specification december 11, 1996 motorola mc68hc05j5 vi rev 1.1 list of figures figure title page
december 11, 1996 general release specification mc68hc05j5 motorola rev 1.1 vii list of tables table title page 4-1 vector address for interrupts and reset.......................................................... 4-1 6-1 mode select summary..................................................................................... 6-1 6-2 cop watchdog timer recommendations ....................................................... 6-5 7-1 port a i/o pin functions................................................................................... 7-7 7-2 port b i/o pin functions................................................................................... 7-7 8-1 rti rates and cop reset times .................................................................... 8-4
general release specification december 11, 1996 motorola mc68hc05j5 viii rev 1.1 list of tables table title page
december 11, 1996 general release specification mc68hc05j5 general description motorola rev 1.1 1-1 section 1 general description the mc68hc05j5 hcmos microcontroller is a member of the mc68hc05 family of low-cost single-chip 8-bit microcontroller units (mcus). the mc68hc05j5 is an enhanced version of the mc68hc05j1a, which includes high sink current port pins, slow output transition port pins, an extra interrupt on a port pin, low-voltage-reset, and a tight tolerance rc oscillator option. the mc68hc05j5 is available in 20-pin and 16-pin packages. (the 16-pin package has four less i/o port lines than the 20-pin package.) although the mc68hc05j5 is an enhanced version of the mc68hc05j1a, their pin assignments are different. 1.1 features industry standard m68hc05 cpu core fully static operation with no minimum clock speed 1240 bytes of user rom 64 bytes of user ram 14 bidirectional i/o pins on-chip oscillator: crystal/resonator oscillator or rc oscillator with only one external resistor required low voltage reset (lvr) hardware mask and ?g for external interrupts 15-bit multi-function timer computer operating properly (cop) watchdog power saving stop and wait modes illegal address reset (iladr) available in 16-pin pdip, 16-pin soic, 20-pin pdip, and 20-pin soic packages
general release specification december 11, 1996 motorola general description mc68hc05j5 1-2 rev 1.1 1.2 mask options the following mask options are available: figure 1-1. mc68hc05j5 block diagram mask option on-chip oscillator [crystal/resonator] or [rc] crystal/resonator feedback resistor [connected] or [disconnected] stop instruction convert to wait [enabled] or [disabled] pa0-pa3 external interrupt capability [enabled] or [disabled] external interrupt pins (irq , pa0-pa3) [edge-triggered] or [edge and level triggered] port a and port b pull-down/pull-up resistors [connected] or [disconnected] cop watchdog timer [enabled] or [disabled] low voltage reset [enabled] or [disabled] oscillator and divide by 2 osc1 64 bytes ram 1240 bytes rom pa0 ? pa1 ? pa2 ? pa3 ? pa4 - pa5 - pa6 ? pa7 data dir reg port a reg irq vdd vss stk ptr cond code reg 1 1 1 i n z c h index reg cpu control 0 0 0 1 1 0 0 0 0 0 alu 68hc05 cpu accum program counter cpu registers osc2/r reset core timer (cop) low voltage reset pb0 pb1 pb2 pb3 2 pb4 2 pb5 2 data dir reg port b reg - : 8 ma current sink : 25 ma current sink, open-drained ? : external edge interrupt capability ? : open-drained with internal pull-up and 8 ma current sink : external interrupt capability, open-drained with internal pull-up and 8 ma current sink 2 : not bonded out in 16-pin package : 25 ma current sink open-drained with internal pull-up and not bonded out in with internal pull-up 16-pin package
december 11, 1996 general release specification mc68hc05j5 general description motorola rev 1.1 1-3 figure 1-2. pin assignments for 16-pin package figure 1-3. pin assignments for 20-pin package osc2/r 1 osc1 2 reset 3 pa7 4 pa6 5 pa5 6 pa4 7 pb0 8 pb1 16 vdd 15 vss 14 irq 13 pa0 12 pa1 11 pa2 10 pa3 9 pb3 1 osc2/r 2 osc1 3 reset 4 pa7 5 pa6 6 pa5 7 pa4 8 pb2 20 pb1 19 vdd 18 vss 17 irq 16 pa0 15 pa1 14 pa2 13 pb0 9 pb4 10 pa3 12 pb5 11
general release specification december 11, 1996 motorola general description mc68hc05j5 1-4 rev 1.1 1.3 functional pin description the following paragraphs give a description of the general function of each pin assigned in figure 1-2 and figure 1-3 . 1.3.1 v dd and v ss power is supplied to the mcu through v dd and v ss . v dd is the positive supply, and v ss is ground. the mcu operates from a single power supply. very fast signal transitions occur on the mcu pins. the short rise and fall times place very high short-duration current demands on the power supply. to prevent noise problems, special care should be taken to provide good power supply bypassing at the mcu by using bypass capacitors with good high-frequency characteristics that are positioned as close to the mcu as possible. bypassing requirements vary, depending on how heavily the mcu pins are loaded. 1.3.2 osc1, osc2/r the osc1 and osc2/r pins are the connections for the on-chip oscillator. the osc1 and osc2/r pins can accept the following sets of components: 1. a crystal as shown in figure 1-4 (a) 2. a ceramic resonator as shown in figure 1-4 (a) 3. an external resistor as shown in figure 1-4 (b) 4. an external clock signal as shown in figure 1-4 (c) the frequency, f osc , of the oscillator or external clock source is divided by two to produce the internal operating frequency, f op . the type of oscillator is selected by a mask option. an internal 2m w resistor may be selected between osc1 and osc2/r by a mask option (crystal/ceramic resonator mode only). if the rc oscillator option is selected, osc1 pin should be connected to a known logic level, either one or zero. 1.3.2.1 crystal oscillator the circuit in figure 1-4 (a) shows a typical oscillator circuit for an at-cut, parallel resonant crystal. the crystal manufacturers recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. the load capacitance values used in the oscillator circuit design should include all stray capacitances. the crystal and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. an internal start-up resistor of approximately 2 m w is provided between osc1 and osc2/r for the crystal type oscillator as a mask option.
december 11, 1996 general release specification mc68hc05j5 general description motorola rev 1.1 1-5 figure 1-4. oscillator connections 1.3.2.2 ceramic resonator oscillator in cost-sensitive applications, a ceramic resonator can be used in place of the crystal. the circuit in figure 1-4 (a) can be used for a ceramic resonator. the resonator manufacturers recommendations should be followed, as the resonator parameters determine the external component values required for maximum stability and reliable starting. the load capacitance values used in the oscillator circuit design should include all stray capacitances. the ceramic resonator and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. an internal start-up resistor of approximately 2 m w is provided between osc1 and osc2/r for the ceramic resonator type oscillator as a mask option. 1.3.2.3 rc oscillator the lowest cost oscillator is the rc oscillator con?uration. with this option an external resistor is connected between osc2/r pin and the v ss pin as shown in figure 1-4 (b). the typical operating frequency f osc is set at 4 mhz with the external r tied to v ss . the internal start-up resistor of approximately 2 m w is not connected between osc1 and osc2/r for the mask option of the rc type oscillator. the tolerance of this rc oscillator is guaranteed to be no greater than 15% at the speci?d conditions of 0 c to 40 c and 5v 10% v dd providing that the tolerance of the external resistor r is at most 1% and the center frequency range is from 3.8mhz to 4.2mhz. the center frequency is the nominal operating frequency of the rc oscillator and can be adjusted by adjusting the external r value to change the internal vco charging current. in order to obtain an oscillator clock with the best possible tolerance, the external resistor connected to the osc2/r pin should be grounded as close to the vss pin as possible and the other terminal of this external resistor should be connected as close to the osc2/r pin as possible. mcu 37 pf osc1 osc2/r 37 pf 2m w r unconnected external clock osc1 osc2/r mcu osc1 osc2/r mcu (a) crystal or ceramic resonator connection (b) rc oscillator connection (c) external clock source connection
general release specification december 11, 1996 motorola general description mc68hc05j5 1-6 rev 1.1 1.3.2.4 external clock an external clock from another cmos-compatible device can be connected to the osc1 input, with the osc2/r input not connected, as shown in figure 1-4 (c). this con?uration is possible only when the crystal/ceramic resonator mask option is selected. 1.3.3 reset this is an i/o pin. this pin can be used as an input to reset the mcu to a known start-up state by pulling it to the low state. the reset pin contains a steering diode to discharge any voltage on the pin to v dd , when the power is removed. an internal pull-up is also connected between this pin and v dd . the reset pin contains an internal schmitt trigger to improve its noise immunity as an input. this pin is an output pin if lvr triggers an internal reset. 1.3.4 irq this input pin drives the asynchronous irq interrupt function of the cpu. the irq interrupt function has a mask option to provide either only negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. if the option is selected to include level-sensitive triggering, the irq input requires an external resistor to v dd for "wired-or" operation, if desired. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. note each of the pa0 to pa3 i/o pins may be connected as an or function with the irq interrupt function by a mask option. this capability allows keyboard scan applications where the transitions or levels on the i/o pins will behave the same as the irq pin, except for the inverted phase. the edge or level sensitivity selected by a separate mask option for the irq pin also applies to the i/o pins or?d to create the irq signal. besides, pa7 also has falling-edge only interrupt capability whose functionality is controlled by another set of register bits. 1.3.5 pa0-pa7 these eight i/o lines comprise port a. pa6 and pa7 are open-drained pins with pull-up devices whereas pa0 to pa5 are push-pull pins with pull-down devices. pa4 to pa7 are also capable of sinking 8 ma. the state of any pin is software programmable and all port a lines are con?ured as inputs during power-on or reset. the lower four i/o pins (pa0 to pa3) can be connected via an internal or gate to the irq interrupt function enabled by a mask option. another independent interrupt source comes from the falling edge on pa7. pa7 interrupt source is associated with a second set of interrupt control/status bits. all port a pins except pa6 and pa7 have software programmable pull-down devices also provided by a mask option. pa6 and pa7 pins have software programmable pull-up devices also provided by the same mask option. pull-up
december 11, 1996 general release specification mc68hc05j5 general description motorola rev 1.1 1-7 devices on pa6 and pa7 once enabled are always enabled regardless of pin direction con?uration, unlike pull-down devices on pa0 to pa5 which are activated only when these pins are con?ured as input pins. pa6 and pa7 pins, when con?ured as output pins, also have slow output falling- edge transition feature to reduce emi. the falling-edge transition time is tentatively set at 250ns typical at a speci?d load of 500pf, assuming the bus rate is 2mhz. the slow transition output feature of pa6 and pa7, along with that of pb1 and pb2, can be enabled or disabled by software. both pa6 and pa7 pins have schmitt trigger input for better noise immunity. v ih and v il are speci?d at 2.4v and 0.8v, respectively. the slow transition feature of pa6 and pa7 pins can be enabled or disabled by software. once enabled, slow transition feature is applied to both pins while in output mode. 1.3.6 pb0-pb5 note i/o lines pb2 to pb5 are not available on the 16-pin package. these six i/o lines comprise port b. pb0, pb3 to pb5 are push-pull i/o lines with pull-down resistor. pb1 and pb2 are open-drain i/o lines with pull-up resistor. the state of any line is software programmable and is con?ured as an input during power-on or reset. i/o lines pb1 and pb2 have software programmable pull-up device whereas pb0, pb3 to pb5 have software programmable pull-down device, by a mask option. pull-up devices on pb1 and pb2 lines once enabled are always enabled regardless of pin direction con?uration; unlike pull-down devices on pb0, pb3-pb5 lines, which are activated only when the pin is con?ured as input pin. similar to pa6 and pa7, pb1 also has a slow output falling transition feature when con?ured as an output line. pb1 has 25ma sink capability at 0.5v v ol . pb2 output is one clock cycle (250ns if bus rate is 2mhz) late than other i/o pins if slow output transition feature is enabled. pb2 has 25ma sink capability at 0.5v v ol . note for the 16-pin package, pb1 and pb2 are bonded to the same pin and is labelled pb1. this pb1 has 50ma sink capability is slow transition feature is enabled and if they are written with the same value at the same write cycle. the falling transition time of pb1 is set at 250ns typical at a speci?d load of 50pf, assuming that the bus rate is 2mhz. the slow transition feature on this pb1 pin is longer than pb1 pin for the 20-pin package.
general release specification december 11, 1996 motorola general description mc68hc05j5 1-8 rev 1.1 note if port data register pb1 and pb2 are not written with the same value, pb1 pin on the 16-pin package will sink 25 ma only and the output transition time will be shorter.
december 11, 1996 general release specification mc68hc05j5 memory motorola rev 1.1 2-1 section 2 memory 2.1 memory map the mc68hc05j5 has 2k-bytes of addressable memory consisting 32 bytes of i/o, 64 bytes of user ram, and 1240 bytes of user rom, as shown in figure 2-1 . figure 2-1. mc68hc05j5 memory map rom reserved for test 8 bytes user vectors (rom) 8 bytes unimplemented 160 bytes 0768 0767 2047 2040 stack user ram 64 bytes reset vector (low byte) reset vector (high byte) swi vector (low byte) swi vector (high byte) irq vector (low byte) irq vector (high byte) timer vector (low byte) timer vector (high byte) $07f7 $07f8 $07f9 $07fa $07fb $07fc $07fd $07fe $07ff $001f $0000 $0100 $00ff 0255 0256 i/o 32 bytes 0032 0031 0000 $07ff $07f0 $07ef $0300 $02ff $00c0 $00bf $0020 $001f $0000 user rom 1232 bytes i/o registers 32 bytes (see figure 2-2 ) 0192 0191 unimplemented 512 bytes $07f6 $07f3 $07f4 $07f5 $07f2 $07f1 $07f0 cop watchdog timer* $07cf $07d0 test rom 32 bytes rom * writing a 0 to bit 0 of $07f0 clears the cop timer. reading $07f0 returns user rom data. reserved for test reserved for test reserved for test reserved for test reserved for test reserved for test reserved for test $07f8 $07f7 2032 2039 1999 2000 2031
general release specification december 11, 1996 motorola memory mc68hc05j5 2-2 rev 1.1 2.2 i/o and control registers the i/o and control registers reside in locations $0000-$001f. the overall orga- nization of these registers is shown in figure 2-2 . the bit assignments for each register are shown in figure 2-3 and figure 2-4 . reading from unimplemented bits will return unknown states, and writing to unimplemented bits will be ignored. figure 2-2. i/o registers memory map 2.3 ram the user ram consists of 64 bytes (including the stack), located from $00c0 to $00ff. the stack begins at address $00ff and proceeds down to $00c0. using the stack area for data storage or temporary work locations requires care to pre- vent it from being overwritten due to stacking from an interrupt or subroutine call. 2.4 rom there are a total of 1240 bytes of user rom on-chip. this includes 1232 bytes of user rom from locations $0300 to $07cf for user program storage and 8 bytes for user vectors from locations $07f8 to $07ff. there are a total of 40 bytes of internal test rom on chip at locations $07d0 to $07ef and from $07f0 to $07f7. port a data register $0000 port b data register $0001 port a data direction register $0004 port b data direction register $0005 timer control & status register $0008 timer counter register $0009 reserved $001f unimplemented (2 bytes) unimplemented (2 bytes) unimplemented (5 bytes) unimplemented (13 bytes) irq control & status register $000a port a pull-down/up register $0010 port b pull-down/up register $0011
december 11, 1996 general release specification mc68hc05j5 memory motorola rev 1.1 2-3 figure 2-3. i/o registers $0000-$000f slowe 0 irqr1 $0003 $0002 unimplemented w r unimplemented w r 0 rt1 rt0 read write $0000 port a data porta w r pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 $0001 port b data portb w r $0004 port a data direction ddra w r ddra0 ddra1 ddra2 ddra3 ddra4 ddra5 ddra6 ddra7 $0009 w r addr 1 0 2 3 4 5 6 7 register timer counter tcr $000c unimplemented w r unimplemented reserved for test $0005 port b data direction ddrb w r $0006 unimplemented w r $0007 unimplemented w r tofe 0 tof $0008 w r timer control & status tcsr $000a irq control & status icsr w r $000b unimplemented w r $000d w r unimplemented $000e w r $000f w r rtie rtifr ddrb0 ddrb1 0 0 pb0 pb1 0 irqf 0 irqr 0 irqf1 irqe1 irqe 0 tofr rtif tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 ddrb2 ddrb3 ddrb4 ddrb5 unimplemented unimplemented pb2 pb3 pb4 pb5
general release specification december 11, 1996 motorola memory mc68hc05j5 2-4 rev 1.1 figure 2-4. i/o registers $0010-$001f port a pulldown/up reg. pdura port b pulldown/up reg. pdurb pura7 unimplemented unimplemented unimplemented unimplemented unimplemented reserved for test test unimplemented read write $0010 w r $0011 w r $0014 unimplemented w r $0019 w r addr 1 0 2 3 4 5 6 7 register $001c w r unimplemented reserved for test $0012 unimplemented w r $0013 unimplemented w r $0015 unimplemented w r $0016 unimplemented w r $0017 w r $0018 w r $001a w r $001b w r $001d w r $001e w r $001f w r pura6 pdra5 pdra4 pdra3 pdra2 pdra1 pdra0 purb1 pdrb0 unimplemented purb2 pdrb3 pdrb4 pdrb5 unimplemented
december 11, 1996 general release specification mc68hc05j5 central processing unit motorola rev 1.1 3-1 section 3 central processing unit the mc68hc05j5 has a 2k memory map. the stack has only 64 bytes. there- fore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00c0 and then wrap-around to $00ff. all other instructions and regis- ters behave as described in this chapter. 3.1 registers the mcu contains ?e registers which are hard-wired within the cpu and are not part of the memory map. these ?e registers are shown in figure 3-1 and are described in the following paragraphs. figure 3-1. mc68hc05 programming model condition code register i accumulator 60 a index register 71 x 4 52 3 stack pointer sp 14 8 15 9 12 13 10 11 pc cc 111 11 0 0 0 0 0 0 0 0 program counter hnzc half-carry bit (from bit 3) interrupt mask negative bit zero bit carry bit
general release specification december 11, 1996 motorola central processing unit mc68hc05j5 3-2 rev 1.1 3.1.1 accumulator (a) the accumulator is a general purpose 8-bit register as shown in figure 3-1 . the cpu uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. the accumulator is not affected by a reset of the device. 3.1.2 index register (x) the index register shown in figure 3-1 is an 8-bit register that can perform two functions: indexed addressing temporary storage in indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. in indexed addressing with an 8-bit offset, the cpu ?ds the operand address by adding the index register content to an 8-bit immediate value. in indexed addressing with a 16-bit offset, the cpu ?ds the operand address by adding the index register con- tent to a 16-bit immediate value. the index register can also serve as an auxiliary accumulator for temporary stor- age. the index register is not affected by a reset of the device. 3.1.3 stack pointer (sp) the stack pointer shown in figure 3-1 is a 16-bit register. in mcu devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. the stack pointer contains the address of the next free location on the stack. during a reset or the reset stack pointer (rsp) instruction, the stack pointer is set to $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled off the stack. when accessing memory, the ten most signi?ant bits are permanently set to 0000000011. the six least signi?ant register bits are appended to these ten ?ed bits to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64 ($40) locations. if 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. a subroutine call occupies two locations on the stack and an interrupt uses ?e loca- tions. 3.1.4 program counter (pc) the program counter shown in figure 3-1 is a 16-bit register. in mcu devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. the program counter contains the address of the next instruction or operand to be fetched.
december 11, 1996 general release specification mc68hc05j5 central processing unit motorola rev 1.1 3-3 normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.1.5 condition code register (ccr) the ccr shown in figure 3-1 is a 5-bit register in which four bits are used to indi- cate the results of the instruction just executed. the ?th bit is the interrupt mask. these bits can be individually tested by a program, and speci? actions can be taken as a result of their states. the condition code register should be thought of as having three additional upper bits that are always ones. only the interrupt mask is affected by a reset of the device. the following paragraphs explain the functions of the lower ?e bits of the condition code register. 3.1.5.1 half carry bit (h-bit) when the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator during the last add or adc (add with carry) operation. the half-carry bit is required for binary-coded decimal (bcd) arithmetic operations. 3.1.5.2 interrupt mask (i-bit) when the interrupt mask is set, the internal and external interrupts are disabled. interrupts are enabled when the interrupt mask is cleared. when an interrupt occurs, the interrupt mask is automatically set after the cpu registers are saved on the stack, but before the interrupt vector is fetched. if an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. normally, the interrupt is processed as soon as the interrupt mask is cleared. a return from interrupt (rti) instruction pulls the cpu registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. after any reset, the interrupt mask is set and can only be cleared by the clear i-bit (cli), or wait instructions. 3.1.5.3 negative bit (n-bit) the negative bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (bit 7 of the result was a logical one.) the negative bit can also be used to check an often tested ?g by assigning the ?g to bit 7 of a register or memory location. loading the accumulator with the contents of that register or location then sets or clears the negative bit according to the state of the ?g.
general release specification december 11, 1996 motorola central processing unit mc68hc05j5 3-4 rev 1.1 3.1.5.4 zero bit (z-bit) the zero bit is set when the result of the last arithmetic operation, logical opera- tion, data manipulation, or data load operation was zero. 3.1.5.5 carry/borrow bit (c-bit) the carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. the carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. this bit is neither set by an inc nor by a dec instruction.
december 11, 1996 general release specification mc68hc05j5 interrupts motorola rev 1.1 4-1 section 4 interrupts the cpu can be interrupted in ?e different ways: non-maskable software interrupt instruction (swi) external asynchronous interrupt (irq ) optional external interrupt on pa0-pa3 (mask option) external interrupt on pa7 internal timer interrupt 4.1 cpu interrupt processing interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. if interrupts are not masked (i-bit in the ccr is clear) and the corresponding interrupt enable bit is set the processor will proceed with interrupt processing. otherwise, the next instruction is fetched and executed. if an interrupt occurs the processor completes the current instruction, then stacks the current cpu register states, sets the i-bit to inhibit further interrupts, and ?ally checks the pending hardware interrupts. if more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location shown in table 4-1 will be serviced ?st. the swi is executed the same as any other instruction, regardless of the i-bit state. when an interrupt is to be processed the cpu fetches the address of the appropriate interrupt software service routine from the vector table at locations $07f8 to $07ff as de?ed in table 4-1 . table 4-1. vector address for interrupts and reset n/a n/a irqf/irqf1 tof rtif register n/a n/a icsr tcsr tcsr flag name interrupts reset software external interrupt timer overflow real time interrupt cpu interrupt reset swi irq timer timer vector address $07fe-$07ff $07fc-$07fd $07fa-$07fb $07f8-$07f9 $07f8-$07f9
general release specification december 11, 1996 motorola interrupts mc68hc05j5 4-2 rev 1.1 an rti instruction is used to signify when the interrupt software service routine is completed. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. figure 4-1 shows the sequence of events that occur during interrupt processing. figure 4-1. interrupt processing flowchart 4.2 reset interrupt sequence the reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in figure 4-1 . a low level input on the reset pin or an internally generated rst signal causes the program to vector to its starting address which is speci?d by the contents of memory locations $07fe and $07ff. the i-bit in the condition code register is also set. execute instruction from reset is i-bit set? load pc from: swi: $07fc, $07fd irq: $07fa-$07fb timer: $07f8-$07f9 set i-bit in ccr stack pc, x, a, cc clear irq request latch if irqe1 is cleared restore registers from stack cc, a, x, pc y n irq external interrupt? y n timer internal interrupt? y n fetch next instruction rti instruction ? y n swi instruction ? y n
december 11, 1996 general release specification mc68hc05j5 interrupts motorola rev 1.1 4-3 4.3 software interrupt (swi) the swi is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the i-bit in the ccr. as with any instruction, interrupts pending during the previous instruction will be serviced before the swi opcode is fetched. the interrupt service routine address is speci?d by the contents of memory locations $07fc and $07fd. 4.4 hardware interrupts all hardware interrupts except reset are maskable by the i-bit in the ccr. if the i-bit is set, all hardware interrupts (internal and external) are disabled. clearing the i-bit enables the hardware interrupts. there are two types of hardware interrupts which are explained in the following sections. 4.4.1 external interrupt (irq ) interrupts from external pins are available on: irq pin pa0 to pa3 pins (enabled by mask option) pa7 pin 4.4.1.1 irq , pa0, pa1, pa2, and pa3 pins if ?dge-only sensitivity is chosen by mask option, the irq interrupt is sensitive to the following cases: 1. falling edge on the irq pin. 2. rising edge on any pa0-pa3 pin with irq enabled (via mask option). if ?dge-and-level sensitivity is chosen, the irq interrupt is sensitive to the following cases: 1. low level on the irq pin. 2. falling edge on the irq pin. 3. high level on any pa0-pa3 pin with irq enabled (via mask option). 4. rising edge on any pa0-pa3 pin with irq enabled (via mask option). the irqe enable bit controls whether an active irqf ?g can generate an irq interrupt sequence. this interrupt is serviced by the interrupt service routine located at the address speci?d by the contents of $07fa and $07fb. the irq latch is automatically cleared by entering the interrupt service routine if irqe1 enable bit is cleared. if irqe1 enable bit is also set, the only way of clearing irqf is by writing a logic one to the irqr acknowledge bit. writing a logic one to the irqr acknowledge bit in the icsr is the other way of clearing irqf ?g, regardless of the status of the irqe1 bit, besides irq vector fetch. this conditional reset of irqf ?g provides a way for the user to differentiate the
general release specification december 11, 1996 motorola interrupts mc68hc05j5 4-4 rev 1.1 interrupt sources from irq and irq1 latches and also to make it hc05j1a compatible if pa7 interrupt is not used. as long as the output state of the irqf ?g bit is active the cpu will continuously re-enter the irq interrupt sequence until the active state is removed or the irqe enable bit is cleared. 4.4.1.2 pa7 pin pa7 interrupt source, if enabled by irqe1 enable bit, triggers irq interrupt on pa7 falling edge only. the irq1 latch (irqf1 ?g) can only be cleared by writing a logic one to the irqr1 acknowledge bit in the icsr. irq vector fetch can not clear irqf1 ?g. irq interrupt caused by pa7 falling edge also vectors to $07fa and $07fb. 4.4.2 irq control/status register (icsr), $0a the irq interrupt function is controlled by the icsr located at $000a. all unused bits in the icsr will read as logic zeros. the irqf, irqf1, irqe1 bits are cleared and irqe bit is set by reset. figure 4-2. irq status & control register irqr 1 - pa7 interrupt acknowledge the irqr1 acknowledge bit clears an irq interrupt triggered by a falling edge on pa7 by clearing the irq1 latch. the irqr1 acknowledge bit will always read as a logic zero. 1 = writing a logic one to the irqr1 acknowledge bit will clear the irq1 latch. 0 = writing a logic zero to the irqr1 acknowledge bit will have no effect on the irq1 latch. irqr - irq interrupt acknowledge the irqr acknowledge bit clears an irq interrupt by clearing the irq latch. the irqr acknowledge bit will always read as a logic zero. 1 = writing a logic one to the irqr acknowledge bit will clear the irq latch. 0 = writing a logic zero to the irqr acknowledge bit will have no effect on the irq latch. 0 irqr1 icsr $000a 1 7 w r 0000000 reset t 6543210 irqe irqf 0 irqr 0 irqf1 irqe1 0 reserved for test
december 11, 1996 general release specification mc68hc05j5 interrupts motorola rev 1.1 4-5 irqf1 - pa7 interrupt request flag writing to the irqf1 ?g bit will have no effect on it. if the additional setting of irqf1 ?g bit is not cleared in the irq service routine and the irqe1 enable bit remains set the cpu will re-enter the irq interrupt sequence continuously until either the irqf1 ?g bit or the irqe1 enable bit is cleared. the irqf1 latch is cleared by reset. 1 = indicates that an irq request triggered by a falling edge on pa7 is pending. 0 = indicates that no irq request triggered by a falling edge on pa7 is pending. the irqf1 ?g bit can only be cleared by writing a logic one to the irqr1 acknowledge bit. doing so before exiting the service routine will mask out additional occurrences of the irqf1. irqf - irq interrupt request flag writing to the irqf ?g bit will have no effect on it. if the additional setting of irqf ?g bit is not cleared in the irq service routine and the irqe enable bit remains set the cpu will re-enter the irq interrupt sequence continuously until either the irqf ?g bit or the irqe enable bit is clear. the irqf latch is cleared by reset. 1 = indicates that an irq request is pending. 0 = indicates that no irq request triggered by pins pa0-3 or irq is pending. the irqf ?g bit is cleared once the irq vector is fetched and if irqe1 is also cleared. if irqe1 is set, then the only way of clearing irqf ?g is by writing a logic one to irqr bit. the irqf ?g bit can be cleared, regardless of the status of the irqe1 bit, by writing a logic one to the irqr acknowledge bit to clear the irq latch and also conditioning the external irq sources to be inactive (if the level sensitive interrupts are enabled via mask option). doing so before exiting the service routine will mask out additional occurrences of the irqf. irqe1 - pa7 interrupt enable the irqe1 bit enables/disables the irqf1 ?g bit to initiate an irq interrupt sequence. 1 = enables irqf1 interrupt, that is, the irqf1 ?g bit can generate an interrupt sequence. execution of the stop or wait instructions will leave the irqe1 bit to be unaffected. 0 = the irqf1 ?g bit cannot generate an interrupt sequence. reset clears the irqe1 enable bit, thereby disabling pa7 interrupts.
general release specification december 11, 1996 motorola interrupts mc68hc05j5 4-6 rev 1.1 irqe - irq interrupt enable the irqe bit enables/disables the irqf ?g bit to initiate an irq interrupt sequence. 1 = enables irqf interrupt, that is, the irqf ?g bit can generate an interrupt sequence. reset sets the irqe enable bit, thereby enabling irq interrupts once the i-bit is cleared. execution of the stop or wait instructions causes the irqe bit to be set in order to allow the external irq to exit these modes. 0 = the irqf ?g bit cannot generate an interrupt sequence. 4.4.3 optional external interrupts (pa0-pa3) the irq interrupt can also be triggered by the inputs on the pa0 to pa3 port pins if enabled by a single mask option. if enabled, the lower four bits of port a can activate the irq interrupt function, and the interrupt operation will be the same as for inputs to the irq pin. this mask option of pa0-3 interrupt allow all of these input pins to be or?d with the input present on the irq pin. all pa0 to pa3 pins must be selected as a group as an additional irq interrupt. all the pa0-3 interrupt sources are also controlled by the irqe enable bit. note the bih and bil instructions will only apply to the level on the irq pin itself, and not to the output of the logic or function with the pa0 to pa3 pins. the state of the individual port a pins can be checked by reading the appropriate port a pins as inputs. note if enabled, the pa0 to pa3 and pa7 pins will cause an irq interrupt regardless of whether these pins are con?ured as inputs or outputs. 4.4.4 timer interrupt (timer) the timer interrupt is generated by the multi-function timer when either a timer over?w or a real time interrupt has occurred as described in section 8 . the interrupt ?gs and enable bits for the timer interrupts are located in the timer control/status register (tcsr) located at $0008. the i-bit in the ccr must be clear in order for the timer interrupt to be enabled. either of these two interrupts will vector to the same interrupt service routine located at the address speci?d by the contents of memory locations $07f8 and $07f9.
december 11, 1996 general release specification mc68hc05j5 resets motorola rev 1.1 5-1 section 5 resets the mcu can be reset from ?e sources: one external input and four internal restart conditions. 5.1 external reset (reset ) the reset pin is the only external source of a reset. this pin is connected to a schmitt trigger input gate to provide an upper and lower threshold voltage sepa- rated by a minimum amount of hysteresis. this external reset occurs whenever the reset pin is pulled below the lower threshold and remains in reset until the reset pin rises above the upper threshold. this active low input will generate the rst signal and reset the cpu and peripherals. this pin is also an output pin whenever the lvr triggers an internal reset. termination of the external reset input or the internal cop watchdog reset or lvr are the only reset sources that can alter the operating mode of the mcu. 5.2 internal resets the four internally generated resets are the initial power-on reset function, the cop watchdog timer reset, the illegal address detector reset and the low voltage reset (lvr). termination of the external reset input or the internal cop watch- dog timer or lvr are the only reset sources that can alter the operating mode of the mcu. the other internal resets will not have any effect on the mode of opera- tion when their reset state ends. 5.2.1 power-on reset (por) the internal por is generated on power-up to allow the clock oscillator to stabi- lize. the por is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). there is an oscillator stabilization delay of 4064 internal processor bus clock cycles (ph2) after the oscillator becomes active. the por will generate the rst signal which will reset the cpu. if any other reset function is active at the end of this 4064 cycle delay, the rst signal will remain in the reset condition until the other reset condition(s) end.
general release specification december 11, 1996 motorola resets mc68hc05j5 5-2 rev 1.1 5.2.2 computer operating properly reset (copr) the internal copr reset is generated automatically (if the cop is enabled) by a time-out of the cop watchdog timer. this time-out occurs if the counter in the cop watchdog timer is not reset (cleared) within a speci? time by a software reset sequence. the cop watchdog timer can be disabled by a mask option. refer to section 8.2 for more information on this time-out feature. cop reset also forces the reset pin low the copr will generate the rst signal which will reset the cpu and other peripherals. also, the copr will establish the mode of operation based on the state of the irq pin at the time the copr signal ends. if the voltage on the irq pin is at the v tst level, the state of the pb0 pin during the last rising edge of the reset pin will determine which test mode (internal or expanded) the mcu will be in. if the voltage at the irq pin is in the normal operating range (v ss to v dd ), the mcu will enter single-chip mode when the copr signal ends. if any other reset function is active at the end of the copr reset signal, the rst signal will remain in the reset condition until the other reset condition(s) end. 5.2.3 illegal address reset (iladr) the internal iladr reset is generated when an instruction opcode fetch occurs from an address which is not implemented in the ram ($00c0 - $00ff) nor rom ($0300-$07ff). the iladr will generate the rst signal which will reset the cpu and other peripherals. if any other reset function is active at the end of the iladr reset signal, the rst signal will remain in the reset condition until the other reset condition(s) end. notice that iladr also forces the reset pin low 5.2.4 low voltage reset (lvr) the internal lvr reset is generated when v dd falls below the speci?d lvr trig- ger value v lv r for at least one t cyc . in typical applications, the power supply decoupling circuit will eliminate negative-going voltage glitches of less than one t cyc . this reset will hold the mcu in the reset state until v dd rises above v lv r . whenever v dd is above v lvr and below 4.5v, the mcu is guaranteed to operate although not within speci?ation. the output from the lvr is connected directly to the internal reset circuitry and also forces the reset pin low. the internal reset will be removed once the power supply voltage rises above v lv r , at which time a normal power-on-reset sequence occurs.
december 11, 1996 general release specification mc68hc05j5 modes of operation motorola rev 1.1 6-1 section 6 modes of operation the mc68hc05j5 has the following operating modes: single-chip mode (scm) and self-check mode. the single-chip mode allows maximum use of pins for on-chip peripheral func- tions. the self-check mode capability of the mc68hc05j5 provides an internal check to determine if the device is functional. this section also provides a description of the low-power modes. 6.1 mode entry the mode entry is done at the rising edge of the reset pin. once the device enters one of the operating modes, the mode can be changed only by external reset not software. at the rising edge of the reset pin, the device latches the states of the irq and pb0 pins and places itself in the speci?d mode. while the reset pin low, all pins are con?ured as single-chip mode. table 6-1 shows the states of irq and pb0 pins for each mode. table 6-1. mode select summary 6.2 single-chip mode (scm) the single-chip mode allows the mcu to function as a self-contained microcon- troller, with maximum use of the pins for on-chip peripheral functions. in the single-chip mode all address and data activity occurs within the mcu and is not available externally. single-chip mode is entered if the irq pin is within the normal operating voltage range when the rising edge of a reset or a cop watchdog reset or an internal lvr reset occurs. in single-chip mode, all i/o port pins are available. mode reset irq pb0 single-chip mode l or h x self-check mode v tst h v tst =1.8xv dd h = v dd l = gnd
general release specification december 11, 1996 motorola modes of operation mc68hc05j5 6-2 rev 1.1 6.3 self-check mode the self-check mode provides an internal check to determine if the device is func- tional. 6.4 low-power modes in each of its con?uration modes the mc68hc05j5 is capable of running in one of several low-power operational modes. the wait and stop instructions provide two modes that reduce the power required for the mcu by stopping various inter- nal clocks and/or the on-chip oscillator. the stop and wait instructions are not normally used if the cop watchdog timer is enabled. a mask option is provided to convert the stop instruction to a halt, which is a wait-like instruction that does not halt the cop watchdog timer but has a recovery delay. the ?w of the stop, halt, and wait modes are shown in figure 6-1 . 6.4.1 stop instruction the stop instruction can result in one of two modes of operation depending on the stop mask option chosen. one option is for the stop instruction to operate like the stop in normal mc68hc05 family members and place the device in the stop mode. the other option is for the stop instruction to behave like a wait instruction (except that the restart time will involve a delay) and place the device in the halt mode. 6.4.1.1 stop mode execution of the stop instruction in this mode (as chosen by a mask option) places the mcu in its lowest power consumption mode. in the stop mode the internal oscillator is turned off, halting all internal processing, including the cop watchdog timer. when the cpu enters stop mode the interrupt ?gs (tof and rtif) and the interrupt enable bits (tofe and rtie) in the tcsr are cleared by internal hard- ware to remove any pending timer interrupt requests and to disable any further timer interrupts. execution of the stop instruction automatically clears the i-bit in the condition code register and sets the irqe enable bit in the irq control/sta- tus register so that the irq external interrupt is enabled. all other registers, including the other bits in the tcsr, and memory remain unaltered. all input/out- put lines remain unchanged. the mcu can be brought out of the stop mode only by an irq external interrupt or an externally generated reset or an lvr reset. when exiting the stop mode the internal oscillator will resume after a 4064 internal processor clock cycle oscil- lator stabilization delay.
december 11, 1996 general release specification mc68hc05j5 modes of operation motorola rev 1.1 6-3 note execution of the stop instruction with the stop mode mask option will cause the oscillator to stop and therefore disable the cop watchdog timer. if the cop watchdog timer is to be used, the stop mode should be changed to the halt mode by choosing the appropriate mask option. see section 6.6 for more details. figure 6-1. stop/halt/wait flowcharts 1. fetch reset vector or 2. service interrupt a. stack b. set i-bit c. vector to interrupt routine wait stop conversion to halt? y n external reset? y n irq external interrupt? y n stop external oscillator, stop internal timer clock, reset start-up delay restart external oscillator, start stabilization delay stop internal processor clock, clear i-bit in ccr, and set irqe in icsr end of stabilization delay? y n irq external interrupt? y n external oscillator active and internal timer clock active restart internal processor clock timer internal interrupt? y n external reset? y n stop halt external reset? y n irq external interrupt? y n external oscillator active and internal timer clock active timer internal interrupt? y n cop internal reset? y n cop internal reset? y n stop internal processor clock, clear i-bit in ccr, and set irqe in icsr stop internal processor clock, clear i-bit in ccr, and set irqe in icsr
general release specification december 11, 1996 motorola modes of operation mc68hc05j5 6-4 rev 1.1 6.4.1.2 halt mode execution of the stop instruction in this mode (as chosen by a mask option) places the mcu in a low-power mode, which consumes more power than the stop mode. in the halt mode the internal processor clock is halted, suspending all processor and internal bus activity. internal timer clocks remain active, permit- ting interrupts to be generated from the timer or a reset to be generated from the cop watchdog timer. execution of the stop instruction automatically clears the i-bit in the condition code register and sets the irqe enable bit in the irq con- trol/status register so that the irq external interrupt is enabled. all other regis- ters, memory, and input/output lines remain in their previous states. the halt mode may be exited when a timer interrupt, an external irq, an lvr reset, or external reset occurs. when exiting the halt mode the internal pro- cessor clock will resume after a delay of one to 4064 internal processor clock cycles. this varied delay time is due to the halt mode testing the oscillator stabi- lization delay timer (a feature of the stop mode) which has been free-running (a feature of the wait mode). note the halt mode is not intended for normal use, but is provided to keep the cop watchdog timer active should the stop instruction opcode be inadvertently executed. 6.4.2 wait mode the wait instruction places the mcu in a low-power mode, which consumes more power than the stop mode. in the wait mode the internal processor clock is halted, suspending all processor and internal bus activity. internal timer clocks remain active, permitting interrupts to be generated from the timer or a reset to be generated from the cop watchdog timer. execution of the wait instruction auto- matically clears the i-bit in the condition code register and sets the irqe enable bit in the irq control/status register so that the irq external interrupt is enabled. all other registers, memory, and input/output lines remain in their previous states. if timer interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode and resume normal operation. the timer may be used to gener- ate a periodic exit from the wait mode. the wait mode may also be exited when an external irq or an lvr reset or an external reset occurs. 6.5 data-retention mode if the lvr mask option is selected and since lvr kicks in whenever v dd is below the speci?d lvr trigger voltage which is higher than that required of the data retention mode, the data retention mode will not exist. data retention mode is only meaningful if lvr mask option is not selected.
december 11, 1996 general release specification mc68hc05j5 modes of operation motorola rev 1.1 6-5 the contents of ram and cpu registers are retained at supply voltages as low as 2.0 vdc. this is called the data-retention mode where the data is held, but the device is not guaranteed to operate. the reset pin must be held low during data-retention mode. 6.6 cop watchdog timer considerations the cop watchdog timer is active in all modes of operation if enabled by a mask option. however, regardless of the mask option chosen, the cop watchdog timer will be disabled if the voltage on the irq pin equals or exceeds the v tst voltage level. thus, emulation of applications that do not service the cop should only be done with devices that have the cop mask option disabled. this prevents the voltage level on the irq pin from enabling the cop which would cause a reset and possibly change the operating mode of the device. if the cop watchdog timer is selected by the mask option, any execution of the stop instruction (either intentional or inadvertent due to the cpu being dis- turbed) will cause the oscillator to halt and prevent the cop watchdog timer from timing out unless the stop to halt conversion feature is enabled. therefore, it is recommended that the stop instruction should be converted to a halt instruc- tion if the cop watchdog timer is enabled. if the cop watchdog timer is selected by the mask option, the cop will reset the mcu when it times out. therefore, it is recommended that the cop watchdog should be disabled for a system that must have intentional uses of the wait mode for periods longer than the cop time-out period. the recommended interactions and considerations for the cop watchdog timer, stop instruction, and wait instruction are summarized in table 6-2 . table 6-2. cop watchdog timer recommendations less than v tst wait time less than cop time-out v tst = 1.8xv dd voltage on irq pin stop instruction wait time then the cop watchdog timer should be as follows: less than v tst disable cop by mask option converted to halt by mask option enable or disable cop by mask option wait time more than cop time-out more than v tst acts as stop or converted to halt by mask option cop is disabled by irq input level any length wait time any length wait time acts as stop less than v tst disable cop by mask option converted to halt by mask option if the following conditions exist:
general release specification december 11, 1996 motorola modes of operation mc68hc05j5 6-6 rev 1.1
december 11, 1996 general release specification mc68hc05j5 input/output ports motorola rev 1.1 7-1 section 7 input/output ports in the single-chip mode there are 14 usable bidirectional i/o lines arranged as one 8-bit i/o port (port a), and one 6-bit i/o port (port b). the individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (ddrs). also, if enabled by a single mask option all port a and port b i/o pins may have individual software programmable pull-down or pull-up devices. also, pa4-pa7 and pb1-pb2 pins have properties of sinking higher current; pa0-pa3 may function as additional irq interrupt input sources. note that both pa6 and pa7 pins have schmitt trigger input for better noise immunity. v ih and v il speci?d at 2.4v and 0.8v, respectively. 7.1 slow output falling-edge transition figure 7-1. port b data direction register slowe - slow transition enabled the slow transition feature is controlled by the slowe bit of ddrb (port b data direction register). 1 = enables the slow falling-edge output transition feature on the four i/o lines: pa6, pa7, pb1, and pb2. if the pin is con?ured as an output pin. 0 = disables slow falling-edge output transition feature on the four i/o lines: pa6, pa7, pb1, and pb2. default value of slowe bit is cleared. 7.2 port a port a is an 8-bit bi-directional port which shares ?e of its pins with the irq interrupt system as shown in figure 7-2 . note that both pa6 and pa7 pins have schmitt trigger input for better noise immunity. only pa6 and pa7 are of open- drained type with slow output transition feature. each port a pin is controlled by 0 ddrb0 ddrb $0005 0 7 w r 0000000 reset t 6543210 slowe ddrb1 ddrb2 ddrb3 ddrb4 ddrb5
general release specification december 11, 1996 motorola input/output ports mc68hc05j5 7-2 rev 1.1 the corresponding bits in a data direction register, a data register, and a pull- down/up register. the port a data register is located at address $0000. the port a data direction register (ddra) is located at address $0004. the port a pull- down/up register (pdura) is located at address $0010. reset clears the ddra and the pdura. the port a data register is unaffected by reset. figure 7-2. port a i/o circuitry 7.2.1 port a data register each port a i/o pin has a corresponding bit in the port a data register. when a port a pin is programmed as an output the state of the corresponding data regis- ter bit determines the state of the output pin. when a port a pin is programmed as an input, any read of the port a data register will return the logic state of the cor- responding i/o pin. the port a data register is unaffected by reset. 7.2.2 port a data direction register each port a i/o pin may be programmed as an input by clearing the correspond- ing bit in the ddra, or programmed as an output by setting the corresponding bit in the ddra. the ddra can be accessed at address $0004. the ddra is cleared by reset. if con?ured as output pins, pa6 and pa7 have slow output falling-edge transition feature. the slow transition feature is controlled by the slowe bit of ddrb. slowe bit, if set and if the pin is con?ured as an output pin, enables the slow falling-edge output transition feature of all three i/o lines, pa6, pa7, and pb1. write $0010 100 m a pull-down read $0000 write $0000 read $0004 data register bit pa0-pa3 and pa7 only: to irq interrupt system 8 ma sink capability (bits 4-7 only) i/o pin output mask option (software pull-down/up inhibit) internal hc05 data bus reset (rst) write $0004 data direction register bit pull-down/up register bit vdd 5k pull-up note: each i/o port pin can have either pull-up and pull-down device, not both pa6 and pa7 output drivers are of open-drained type
december 11, 1996 general release specification mc68hc05j5 input/output ports motorola rev 1.1 7-3 7.2.3 port a pull-down/up register all port a i/o pins may have software programmable pull-down/up devices enabled by the applicable mask option. if the pull-down/up mask option is selected, the pull-down/up is activated whenever the corresponding bit in the pdura is clear. if the corresponding bit in the pdura bit is set or the mask option for pull-down/up is not chosen, the pull-down/up will be disabled. a pull- down on an i/o pin is activated only if the i/o pin is programmed as an input whereas a pull-up device on an i/o pin is always activated whenever enabled, regardless of port direction. the pdura is a write-only register. any reads of location $0010 will return unde- ?ed results. since reset clears both the ddra and the pdura, all pins will ini- tialize as inputs with the pull-down active and pull-up devices active (if enabled by mask option). typical value of port a pull-up is 5k w . 7.2.4 port a drive capability the outputs for the upper four bits of port a (pa4, pa5, pa6 and pa7) are capable of sinking approximately 8 ma of current to v ss . 7.2.5 port a i/o pin interrupts the inputs to pa0, pa1, pa2, pa3 may be connected to the irq input of the cpu if enabled by a mask option. the input to pa7 is also connected to the irq input of the cpu, yet it is only enabled or disabled by software, not by mask option. pa7 interrupt capability is controlled by a set of control and status bits (irqe1, irqf1, irqr1), different from the set of control and status bits for that of pa0-pa3 and irq pin (irqe, irqf, irqr) in the same icsr (interrupt control and status reg- ister). when connected as an alternate source of an irq interrupt, pa0-3 input pins will behave the same as the irq pin itself, except that their active state is a logical one or a rising edge. the irq pin has an active state that is a logical zero or a falling edge. pa7 interrupt occurs, if enabled, only upon the falling edge at the input. if mask options for both level and edge sensitivity interrupts are chosen, the pres- ence of a logic one or occurrence of a rising edge on any one of the lower four port a pins will cause an irq interrupt request. if the edge-only sensitivity is selected, the occurrence of a rising edge on any one of the lower four port a pins will cause an irq interrupt request. as long as any one of the lower four port a irq inputs remains at a logic one level, the other of the lower four port a irq inputs are effectively ignored.
general release specification december 11, 1996 motorola input/output ports mc68hc05j5 7-4 rev 1.1 note the bih and bil instructions will only apply to the level on the irq pin itself, and not to the internal irq input to the cpu. therefore bih and bil cannot be used to test the state of the lower four port a input pins as a group nor that of pa7. 7.3 port b port b is a 6-bit bidirectional port which functions as shown in figure 7-3 . each port b pin is controlled by the corresponding bits in a data direction register, a data register, and a pull-down/up register. the port b data register is located at address $0001. the port b data direction register (ddrb) is located at address $0005. the port b pull-down/up register (pdurb) is located at address $0011. reset clears the ddrb and the pdurb. the port b data register is unaffected by reset. pb1 and pb2 are open-drained type i/os, capable of typically sinking 25ma current each, at v ol 0.5v max. for the 16-pin package, pb1 and pb2 are connected together to form the pin labelled pb1 on the package. this pb1 pin will have a maximum sink current of 50ma if both pb1 and pb2 are written with the same value at the same write cycle. figure 7-3. port b i/o circuitry write $0011 read $0001 write $0001 read $0005 write $0005 internal hc05 data bus 100 m a pull-down data register bit i/o pin output mask option (software pull-down/up inhibit) reset (rst) data direction register bit pull-down/up register bit vdd 100k pull-up note: each i/o port pin can have either pull-up and pull-down device not both pb1 and pb2 output drivers are of open-drained type
december 11, 1996 general release specification mc68hc05j5 input/output ports motorola rev 1.1 7-5 7.3.1 port b data register all port b i/o pins have a corresponding bit in the port b data register. when a port b pin is programmed as an output the state of the corresponding data regis- ter bit determines the state of the output pin. when a port b pin is programmed as an input, any read of the port b data register will return the logic state of the cor- responding i/o pin. the port b data register is unaffected by reset. unused bits 6 and 7 will always read as logic zeros, and any write to these bits will be ignored. the port b data register is unaffected by reset. 7.3.2 port b data direction register port b i/o pins may be programmed as an input by clearing the corresponding bit in the ddrb, or programmed as an output by setting the corresponding bit in the ddrb. the ddrb can be accessed at address $0005. unused bits 6 and 7 will always read as logic zeros, and any write to these bits will be ignored.the ddrb is cleared by reset. if con?ured as output pins, pb1 and pb2 have slow output falling-edge transition feature. the slow transition feature is controlled by the slowe bit of ddrb. slowe bit, if set and if the pin is con?ured as an output pin, enables the slow falling-edge output transition feature of all four i/o lines, pa6, pa7, pb1 and pb2. for the 16-pin package type, care should be taken in using pb1 pin, which is bonded to two internal port b i/o lines pb1 and pb2, to constitute a 50 ma current sinking driver. both pb1 and pb2 i/o lines are capable of sinking 25 ma. if they are written with the same logic 0 value in the same write cycle, pb1 pin will sink 50 ma. if they are written with different values in the same write cycle, pb1 pin will sink only 25 ma. for the 20-pin package type, i/o lines pb1 and pb2 are not bonded to the same pin. hence, to constitute a 50ma current sinking driver, pb1 and pb2 pins have to be tied together externally and controlled in the same way as in the16-pin pack- age type case. also, if the slow transition feature of pin pb1 is enabled, a combination of i/o lines pb1 and pb2, is also a combination of slow transition features of i/o lines pb1 and pb2. pb2 line falling-edge output transition occurs t cyc /2 after the write cycle, with a standard i/o edge transition time. whereas for pb1 line, the falling- edge transition occurring immediately after the write cycle, but with an edge transition time slower than standard i/os, similar to pa6 and pa7 pins. the net result is, for the 16-pin package type, since both pb1 and pb2 i/o lines are bonded to the same pb1 pin, the combination of delayed pb1 line sharp-edge output and the non-delayed slow transition output yields the desired slow output falling-edge transition. for the 20-pin package, pb1 and pb2 pins should be tied externally to create a driver with the desired slow output falling-edge transition feature. if slowe is set and pb2 pin is not tied to pb1 pin, be advised that the output at pb2 changes state t cyc /2 after the write cycle.
general release specification december 11, 1996 motorola input/output ports mc68hc05j5 7-6 rev 1.1 7.3.3 port b pull-down/up register all port b i/o pins may have software programmable pull-down/up devices enabled by a mask option. if the pull-down/up mask option is selected, the pull- down/up is activated whenever the corresponding bit in the pdurb is clear. a pull-down on an i/o pin is activated only if the i/o pin is programmed as an input whereas a pull-up device on an i/o pin is always activated whenever enabled, regardless of port direction. the pdurb is a write-only register. any reads of location $0011 will return unde- ?ed results. since reset clears both the ddrb and the pdurb, all pins will ini- tialize as inputs with the pull-down devices active and pull-up devices active (if chosen via mask option). typical value of port b pull-up is 100k w . 7.4 i/o port programming all i/o pins can be programmed as inputs or outputs, with or without pull-down/up devices. 7.4.1 pin data direction the direction of a pin is determined by the state of its corresponding bit in the associated port data direction register (ddr). a pin is con?ured as an output if its corresponding ddr bit is set to a logic one. a pin is con?ured as an input if its corresponding ddr bit is cleared to a logic zero. the data direction bits ddrb0 to ddrb2 and ddra0 to ddra7 are read/write bits which can be manipulated with read-modify-write instructions. at power-on or reset, all ddrs are cleared which con?ures all port pins as inputs. if the pull- down/up mask option is chosen, all pins will initially power-up with their software programmable pull-downs/ups enabled. 7.4.2 output pin when an i/o pin is programmed as an output pin, the state of the corresponding data register bit will determine the state of the pin. the state of the data register bits can be altered by writing to address $0000 for port a and address $0001 for port b. reads of the corresponding data register bit at address $0000 or $0001 will return the state of the data register bit (not the state of the i/o pin itself). therefore bit manipulation is possible on all pins programmed as outputs. if the corresponding bit in the pull-down/up register is clear (and the pull-down/up mask option is chosen), only output pins with pull-ups have an activated pull-up device connected to the pin. for those pins with pull-downs and con?ured as out- put pins, the pull-downs will be inactivated regardless of the state of the corre- sponding pull-down/up register bit. since the pull-down/up register bits are write- only, bit manipulation should not be used on these register bits.
december 11, 1996 general release specification mc68hc05j5 input/output ports motorola rev 1.1 7-7 7.4.3 input pin when an i/o pin is programmed as an input pin, the state of the pin can be deter- mined by reading the corresponding data register bit. any writes to the corre- sponding data register bit for an input pin will be ignored in the sense that the written value will not be re?cted on the pin, rather it is only re?cted in the port data register. please refer to table 7-1 and table 7-2 for details. if the corresponding bit in the pull-down/up register is clear (and the pull-down/up mask option is chosen) the input pin will also have an activated pull-down/up device. since the pull-down/up register bits are write-only, bit manipulation should not be used on these register bits. 7.4.4 i/o pin transitions a "glitch" can be generated on an i/o pin when changing it from an input to an out- put unless the data register is ?st preconditioned to the desired state before changing the corresponding ddr bit from a zero to a one. if pull-downs are enabled by mask option, a ?ating input can be avoided by clear- ing the pull-down/up register bit before changing the corresponding ddr from a one to a zero. this will insure that the pull-down device will be activated before the i/o pin changes from a driven output to a pulled low/high input. 7.4.5 i/o pin truth tables every pin on port a and port b may be programmed as an input or an output under software control as shown in table 7-1 and table 7-2 . all port i/o pins may also have software programmable pull-down/up devices if selected by the appropriate mask option. table 7-1. port a i/o pin functions table 7-2. port b i/o pin functions accesses to pdura at $0010 accesses to data register @ $0000 0 1 in, hi-z out pdura0-7 pdura0-7 ddra0-7 ddra0-7 i/o pin pa0-7 * pa0-7 u u i/o pin mode ddra read/write accesses to ddra @ $0004 read write read write * does not affect input, but stored to data register u is undefined accesses to pdurb at $0011 accesses to data register @ $0001 0 1 in, hi-z out pdurb0-2 pdurb0-2 ddrb0-2 ddrb0-2 i/o pin pb0-2 * pb0-2 u u i/o pin mode ddra read/write accesses to ddrb @ $0005 read write read write * does not affect input, but stored to data register u is undefined
general release specification december 11, 1996 motorola input/output ports mc68hc05j5 7-8 rev 1.1
december 11, 1996 general release specification mc68hc05j5 multi-function timer motorola rev 1.1 8-1 section 8 multi-function timer the mc68hc05j5 timer is a 15-stage multi-function ripple counter. the features include timer over flow (tof), power-on reset (por), real time interrupt (rti), and cop watchdog timer. figure 8-1. multi-function timer block diagram as shown in figure 8-1 , the timer is driven by the timer clock, ntf1, divided by four (4). ntf1 has the same phase and frequency as the processor bus clock, ph2, but is not stopped by the wait or halt modes. this signal drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time by accessing the timer counter register (tcr) at address $09. a timer over- ?w function is implemented on the last stage of this counter, giving a possible cop clear mc68hc05 internal bus $09 tcr 7-bit counter interrupt circuit $08 tcsr rti select circuit overflow circuit detect cop watchdog timer to reset logic to interrupt logic 8 8 f op /2 2 f op /2 10 por tcbp tcsr tcr internal timer clock (ntf1) tof rtif tofe rtie rt1 rt0 rtifr tofr timer control & status register timer counter register (tcr) ? 4 ? 8
general release specification december 11, 1996 motorola multi-function timer mc68hc05j5 8-2 rev 1.1 interrupt at the rate of f op /1024. two additional stages produce the por function at f op /4064. the timer counter bypass circuitry (available only in expanded test mode) is at this point in the timer chain. this circuit is followed by two more stages, with the resulting clock (f op /16384) driving the real time interrupt circuit. the rti circuit consists of three divider stages with a 1 of 4 selector. the output of the rti circuit is further divided by eight to drive the optional cop watchdog timer circuit, which can be enabled by a mask option. the rti rate selector bits, and the rti and tof enable bits and ?gs are located in the timer control and status register at location $08. the real time interrupt circuit consists of a three stage divider and a 1 of 4 selec- tor. the clock frequency that drives the rti circuit is f op /2 14 (or f op /16384) with three additional divider stages giving a maximum interrupt period of f op /2 17 (or f op / 131072). the power-on cycle clears the entire counter chain and begins clocking the counter. after 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. at this point, if reset is not asserted, the timer will start counting up from zero and normal device operation will begin. if reset is asserted at any time during operation the counter chain will be cleared. 8.1 timer registers the 15-stage multi-function timer contains two registers: a timer counter regis- ter and a timer control/status register. 8.1.1 timer counter register (tcr), $09 the timer counter register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. this counter is clocked at f op divided by 4 and can be used for various functions including a soft- ware input capture. extended time periods can be attained using the tof function to increment a temporary ram storage location thereby simulating a 16-bit (or more) counter. the value of each bit of the tcr is shown in figure 8-2 . this reg- ister is cleared by reset. figure 8-2. timer counter register tcr $09 0 7 w r 0000000 reset t 6543210 tmr0 tmr2 tmr1 tmr3 tmr4 tmr5 tmr6 tmr7
december 11, 1996 general release specification mc68hc05j5 multi-function timer motorola rev 1.1 8-3 8.1.2 timer control/status register (tcsr), $08 the tcsr contains the timer interrupt ?g bits, the timer interrupt enable bits, and the real time interrupt rate select bits. bit 2 and bit 3 are write-only bits which will read as logical zeros. figure 8-3 shows the value of each bit in the tcsr follow- ing reset. figure 8-3. timer control/status register (tcsr) tof - timer over?w flag the tof is a read-only ?g bit. 1 = set when the 8-bit ripple counter rolls over from $ff to $00. a timer interrupt request will be generated if tofe is also set. 0 = reset by writing a logical one to the tof acknowledge bit, tofr. writing to the tof ?g bit has no effect on its value. this bit is cleared by reset. rtif - real time interrupt flag the rtif is a read-only ?g bit. 1 = set when the output of the chosen (1 of 4 selections) real time interrupt stage goes active. a timer interrupt request will be generated if rtie is also set. 0 = reset by writing a logical one to the rtif acknowledge bit, rtifr. writing to the rtif ?g bit has no effect on its value. this bit is cleared by reset. tofe - timer over?w enable the tofe is an enable bit that allows generation of a timer interrupt upon over?w of the timer counter register. 1 = when set, the timer interrupt is generated when the tof ?g bit is set. 0 = when cleared, no timer interrupt caused by tof bit set will be generated. this bit is cleared by reset. rtie - real time interrupt enable the rtie is an enable bit that allows generation of a timer interrupt by the rtif bit. 1 = when set, the timer interrupt is generated when the rtif ?g bit is set. 0 = when cleared, no timer interrupt caused by rtif bit set will be generated. this bit is cleared by reset. rtif tofe 0 7 tof rt1 w r 0000011 6543210 tcsr $08 reset t 0 rtifr 0 tofr rtie rt0
general release specification december 11, 1996 motorola multi-function timer mc68hc05j5 8-4 rev 1.1 tofr - timer over?w acknowledge the tofr is an acknowledge bit that resets the tof ?g bit. this bit is unaf- fected by reset. reading the tofr will always return a logical zero. 1 = clears the tof ?g bit. 0 = does not clear the tof ?g bit. rtifr - real time interrupt acknowledge the rtifr is an acknowledge bit that resets the rtif ?g bit. this bit is unaf- fected by reset. reading the rtifr will always return a logical zero. 1 = clears the rtif ?g bit. 0 = does not clear the rtif ?g bit. rt1:rt0 - real time interrupt rate select the rt0 and rt1 control bits select one of four taps for the real time interrupt circuit. table 8-1 shows the available interrupt rates for two f op values. both the rt0 and rt1 control bits are set by reset, selecting the lowest periodic rate and therefore the maximum time in which to alter these bits if necessary. care should be taken when altering rt0 and rt1 if the time-out period is imminent or uncertain. if the selected tap is modi?d during a cycle in which the counter is switching, an rtif could be missed or an additional one could be generated. to avoid problems, the cop should be cleared just prior to changing rti taps. table 8-1. rti rates and cop reset times 8.2 cop watchdog timer the cop (computer operating properly) watchdog timer function is imple- mented on this device by using the output of the rti circuit and further dividing it by eight. the minimum cop reset times are listed in table 8-1 . if the cop circuit times out, an internal reset is generated and the reset vector is fetched. prevent- ing a cop time-out is done by writing a logical zero to bit 0 of address $07f0 as shown in figure 8-4 . the cop register is shared with a test rom byte. this address location is not affected by any reset signals. reading this location will return the test rom byte. when the cop is cleared, only the ?al divide by eight stage (output of the rti) is cleared. the cop watchdog timer can be enabled/ disabled by a mask option. rt1:rt0 1.000 mhz 2.000 mhz 00 32.768 ms 16.384 ms 01 65.536 ms 32.768 ms 10 131.072 ms 65.536 ms 11 rti rates at f op freq. specified: 16.384 ms 8.192 ms divider 32768 65536 131072 16384 divider 262144 524288 1048576 131072 1.000 mhz 2.000 mhz 262 ms 131 ms 524 ms 262 ms 1.059 s 524 ms 131 ms 66 ms min. cop reset at f op freq. specified:
december 11, 1996 general release specification mc68hc05j5 multi-function timer motorola rev 1.1 8-5 figure 8-4. cop watchdog timer location 8.3 operation during stop mode the timer system is cleared when going into stop mode. when stop is exited by an external interrupt or an lvr reset or an external reset , the internal oscilla- tor will resume, followed by a 4064 internal processor oscillator stabilization delay. the timer system counter is then cleared and operation resumes. if chosen by a mask option, the stop instruction will initiate halt mode and the effects on the timer are as described in section 8.4 . 8.4 operation during wait/halt mode the cpu clock halts during the wait/halt mode, but the timer remains active. if interrupts are enabled, a timer interrupt or custom periodic interrupt will cause the processor to exit the wait/halt mode. 7 w r 6543210 cop $07f0 copr reading $07f0 returns the contents of test rom. unimplemented
general release specification december 11, 1996 motorola multi-function timer mc68hc05j5 8-6 rev 1.1
december 11, 1996 general release specification mc68hc05j5 instruction set motorola rev 1.1 9-1 section 9 instruction set the mcu has a set of 62 basic instructions. they can be divided into ?e different types: register/memory, read-modify-write, branch, bit manipulation, and control. the following paragraphs brie? explain each type. for more information on the instruction set, refer to the m6805 family users manual (m6805um/ad2) or the associated mc68hc05 data sheet. 9.1 register/memory instructions most of these instructions use two operands. one operand is either the accumula- tor or the index register. the other operand is obtained from memory using one of the addressing modes. the jump unconditional (jmp) and jump to subroutine (jsr) instructions have no register operand. refer to the following instruction list. function load a from memory load x from memory store a in memory store x in memory add memory to a add memory and carry to a subtract memory subtract memory from a with borrow and memory to a or memory with a exclusive or memory with a arithmetic compare a with memory arithmetic compare x with memory bit test memory with a (logical compare) jump unconditional jump to subroutine mnemonic lda ldx sta stx add adc sub sbc and ora eor cmp cpx bit jmp jsr multiply mul
general release specification december 11, 1996 motorola instruction set mc68hc05j5 9-2 rev 1.1 9.2 read-modify-write instructions these instructions read a memory location or a register, modify or test its con- tents, and write the modi?d value back to memory or to the register. the test for negative or zero (tst) instruction is an exception to the read-modify-write sequence since it does not modify the value. do not use these read-modify-write instructions on write-only locations. refer to the following list of instructions. 9.3 branch instructions this set of instructions branches if a particular condition is met; otherwise, no operation is performed. branch instructions are two-byte instructions. refer to the following list for branch instructions. function mnemonic increment inc decrement dec clear clr complement com negate (two? complement) neg rotate left to carry rol rotate right to carry ror logical shift left lsl logical shift right lsr arithmetic shift right asr arithmetic shift left asl test for negative or zero tst function mnemonic branch always bra branch never brn branch if higher bhi branch if lower or same bls branch if carry clear bcc branch if higher or same bhs branch if carry set bcs branch if lower blo branch if not equal bne branch if equal beq branch if half carry clear bhcc branch if half carry set bhcs branch if plus bpl branch if minus bmi branch if interrupt mask bit is clear bmc branch if interrupt mask bit is set bms branch if interrupt line is low bil branch if interrupt line is high bih branch to subroutine bsr
december 11, 1996 general release specification mc68hc05j5 instruction set motorola rev 1.1 9-3 9.4 bit manipulation instructions the mcu is capable of setting or clearing any read/write bit which resides in the ?st 256 bytes of the memory space where all port registers, module registers, and part or all of on-chip ram reside. an additional feature allows the software to test and branch on the state of any bit within these 256 locations. the bit set, bit clear, and bit test and branch functions are each implemented with a single instruction. for test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. the bit set and bit clear instructions are also read-modify-write instructions and should not be used to manipulate write-only locations. refer to the following list for bit manipulation instructions. 9.5 control instructions these instructions are register reference instructions and are used to control pro- cessor operation during program execution. refer to the following list for control instructions. 9.6 addressing modes the mcu uses ten different addressing modes to provide the programmer with an opportunity to optimize the code for all situations. the various indexed addressing modes make it possible to locate data tables, code conversion tables, and scaling function set bit n clear bit n mnemonic bset n (n = 0. . .7) bclr n (n = 0. . .7) branch if bit n is set branch if bit n is clear brset n (n = 0. . .7) brclr n (n = 0. . .7) function transfer a to x transfer x to a set carry bit clear carry bit mnemonic tax txa sec clc set interrupt mask bit sei clear interrupt mask bit cli software interrupt swi return from subroutine rts return from interrupt rti reset stack pointer rsp no-operation nop wait wait stop stop
general release specification december 11, 1996 motorola instruction set mc68hc05j5 9-4 rev 1.1 tables anywhere in the memory space. short indexed accesses are single byte instructions; the longest instructions (three bytes) permit accessing tables throughout memory. short and long absolute addressing is also included. one- or two-byte direct addressing instructions access all data bytes in most applications. extended addressing permits jump instructions to reach all memory. the term "effective address" (ea) is used in describing the various addressing modes. effective address is de?ed as the address from which the argument for an instruction is fetched or stored. 9.6.1 immediate in the immediate addressing mode, the operand is contained in the byte immedi- ately following the opcode. the immediate addressing mode is used to access constants that do not change during program execution (e.g., a constant used to initialize a loop counter). 9.6.2 direct in the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. direct addressing allows the user to directly address the lowest 256 bytes in memory with single two-byte instructions. 9.6.3 extended in the extended addressing mode, the effective address of the argument is con- tained in the two bytes following the opcode byte. instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. when using the motorola assembler, the user need not specify whether an instruction uses direct or extended addressing. the assembler automatically selects the shortest form of the instruction. 9.6.4 relative the relative addressing mode is only used in branch instructions. in relative addressing, the contents of the 8-bit signed offset byte (which is the last byte of the instruction) is added to the pc if, and only if, the branch conditions are true. otherwise, control proceeds to the next instruction. the span of relative address- ing is from -128 to +127 from the address of the next opcode. the programmer need not calculate the offset when using the motorola assembler, since it calcu- lates the proper offset and checks to see that it is within the span of the branch. 9.6.5 indexed, no offset in the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. this addressing mode can access the ?st 256 memory locations. these instructions are only one byte long. this mode is often used to move a pointer through a table or to hold the address of a frequently referenced ram or i/o location.
december 11, 1996 general release specification mc68hc05j5 instruction set motorola rev 1.1 9-5 9.6.6 indexed, 8-bit offset in the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. the addressing mode is useful for selecting the kth element in an ele- ment table. with this two-byte instruction, k would typically be in x with the address of the beginning of the table in the instruction. as such, tables may begin anywhere within the ?st 256 addressable locations and could extend as far as location 510. $1fe is the highest location which can be accessed in this way. 9.6.7 indexed, 16-bit offset in the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes fol- lowing the opcode. this address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be any- where in memory. as with direct and extended addressing, the motorola assem- bler determines the shortest form of indexed addressing. 9.6.8 bit set/clear in the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode speci?s the direct address of the byte in which the speci?d bit is to be set or cleared. any read/write register bit in the ?st 256 locations of memory, including i/o, can by selectively set or cleared with a single two-byte instruction. 9.6.9 bit test and branch the bit test and branch addressing mode is a combination of direct addressing and relative addressing. the bit that is to be tested and its condition (set or clear), is included in the opcode. the address of the byte to be tested is in the single byte immediately following the opcode byte. the signed relative 8-bit offset in the third byte is added to the pc if the speci?d bit is set or cleared in the speci?d mem- ory location. this single three-byte instruction allows the program to branch based on the condition of any readable bit in the ?st 256 locations of memory. the span of branching is from -128 to +127 from the address of the next opcode. the state of the tested bit is also transferred to the carry bit of the condition code register. 9.6.10 inherent in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. operations specifying only the index regis- ter and/or accumulator as well as the control instructions with no other arguments are included in this mode. these instructions are one byte long.
general release specification december 11, 1996 motorola instruction set mc68hc05j5 9-6 rev 1.1
december 11, 1996 general release specification mc68hc05j5 electrical specifications motorola rev 1.1 10-1 section 10 electrical specifications 10.1 maximum ratings (voltages referenced to v ss ) this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of opera- tion is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either v ss or v dd ). 10.2 thermal characteristics rating symbol value unit supply voltag ev dd ?.3 to +7.0 v input voltage v in v ss ?.3 to v dd +0.3 v expanded test mode (irq pin only) v in v ss ?.3 to 2v dd +0.3 v current drain per pin excluding pb1, pb2, v dd and v ss i ?5 ma operating temperature range (standard) (extended) t a t l to t h 0 to +70 ?0 to +85 c storage temperature range t stg ?5 to +150 c characteristic symbol value unit thermal resistance plastic soic q ja 60 60 c/w c/w
general release specification december 11, 1996 motorola electrical specifications mc68hc05j5 10-2 rev 1.1 10.3 dc electrical characteristics (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?0 c to +85 c, unless otherwise noted) characteristic symbol min typ max unit output voltage i load = 10.0 m a v ol v oh v dd ?.1 0.1 v v output high voltage (i load = -0.8 ma) pa0-5, pb0, pb3-5 v oh v dd ?.8 v output low voltage (i load = 1.6 ma) pa0-3, pb0, pb3-5 (i load = 8.0 ma) pa4-pa7 (i load = 25.0 ma) pb1, pb2 (note 8) v ol 0.4 0.4 0.5 v input high voltage pa0-5, pb0-5, irq , reset , osc1 v ih 0.7 v dd ? dd v input low voltage pa0-5, pb0-5, irq , reset , osc1 v il v ss 0.2 v dd v positive-going input threshold voltage pa6, pa7 (note 9) v t+ 1.7 v negative-going input threshold voltage pa6, pa7 (note 9) v t 1.15 v supply current (see notes) run wait stop (lvr on) 25 c ?0 c to +85 c stop (lvr off) 25 c ?0 c to +85 c i dd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma ma m a m a m a m a i/o ports hi-z leakage current pa0-7, pb0-5 (without individual pull-down/up activated) i il 10 m a input pull-down current pa0-5, pb0, pb3-5 (with individual pull-down activated) i il 50 100 200 m a input current reset , irq , osc1 i in 1 m a capacitance ports (as input or output) rese t , irq , osc1, osc2/r c out c in 12 8 pf pf crystal/ceramic resonator oscillator mode internal resistor osc1 to osc2/r r osc 1.0 2.0 3.0 m w pull-up resistor pa6, pa7 (note 10) pb1, pb2 r pullup 2 25 5 100 10 200 k w k w lvr trigger voltage v lvr tbd 2.8 tbd v
december 11, 1996 general release specification mc68hc05j5 electrical specifications motorola rev 1.1 10-3 notes: 1. all values shown reflect average measurements. 2. typical values at midpoint of voltage range, 25 c only. 3. wait i dd : only timer system (mft) active. 4. run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 (f osc = 2.0 mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50pf on all outputs, c l = 20 pf on osc2/r. 5. wait, stop i dd : all ports configured as inputs, v il = 0.2 vdc, v ih = v dd ?.2 vdc. 6. stop i dd measured with osc1 = v ss . 7. wait i dd is affected linearly by the osc2/r capacitance. 8. t a = 0 c to +40 c. 9. minimum and maximum values of both v t+ and v t will be determined after enough characterization has been done. input voltage level on pa6 or pa7 higher than 2.4v is guaranteed to be recognized as a logical one and as a logic zero if lower than 0.8v. 10. pa6 and pa7 pull-up resistor values are specified under the condition that pin voltage ranges from 0v to 2.4v. 10.4 control timing (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?0 c to +85 c, unless otherwise noted) notes: 1. the minimum period t ilil or t ihih should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . 2. effects of processing, temperature, and supply voltage (excluding tolerances of external r and c). 3. rc oscillator: typical center frequency is 4.0 mhz. for the specified range of the operating center frequency from 3.8mhz (min) to 4.2 mhz (max), the frequency tolerance is guaranteed to be no more than 15% under the conditions that v dd = 5.0 vdc 10%, t a = 0 c to +40 c and the tolerance of the external r is at most 1%. characteristic symbol min max units frequency of operation rc oscillator option (note 3) crystal oscillator option external clock source f osc 3.8 dc 4.2 4.2 4.2 mhz mhz mhz internal operating frequency crystal oscillator (f osc ? 2 ) rc oscillator (f osc ? 2 ) (note 3) external clock (f osc ? 2 ) f op 1.9 dc 2.1 2.1 2.1 mhz mhz mhz cycle time (1/f op )t cyc 415 ns reset pulse width low t rl 1.5 t cyc irq interrupt pulse width low (edge-triggered) t ilih 0.5 t cyc irq interrupt pulse period t ilil note 1 t cyc pa0 to pa3 interrupt pulse width high (edge-triggered) t ihil 0.5 t cyc pa0 to pa3 interrupt pulse period t ihih note 1 t cyc pa7 interrupt pulse width low t ilih 0.5 t cyc osc1 pulse width t oh , t ol 200 ns output high to low transition period on pa6, pa7, pb1 t slow tbd tbd ns
general release specification december 11, 1996 motorola electrical specifications mc68hc05j5 10-4 rev 1.1
december 11, 1996 general release specification mc68hc05j5 mechanical specification motorola rev 1.1 11-1 section 11 mechanical specification this section provides the mechnical dimensions for the four available packages for mc68hc05j5. 11.1 16-pin plastic dual-in-line package (pdip) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. style 1: pin 1. cathode 2. cathode 3. cathode 4. cathode 5. cathode 6. cathode 7. cathode 8. cathode 9. anode 10. anode 11. anode 12. anode 13. anode 14. anode 15. anode 16. anode style 2: pin 1. common drain 2. common drain 3. common drain 4. common drain 5. common drain 6. common drain 7. common drain 8. common drain 9. gate 10. source 11. gate 12. source 13. gate 14. source 15. gate 16. source a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
general release specification december 11, 1996 motorola mechanical specification mc68hc05j5 11-2 rev 1.1 11.2 16-pin small outline intergrated circuit (soic) 11.3 20-pin plastic dual-in-line package (pdip) (case 738-03) dim min max min max inches millimeters a 10.15 10.45 0.400 0.411 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 m b m 0.010 (0.25) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b p 8x g 14x d 16x seating plane t s a m 0.010 (0.25) b s t 16 9 8 1 f j r x 45 m c k

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december 11, 1996 general release specification mc68hc05j5 mechanical specification motorola rev 1.1 11-3 11.4 20-pin small outline intergrated circuit (soic) (case 751d-04)

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general release specification december 11, 1996 motorola mechanical specification mc68hc05j5 11-4 rev 1.1
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